1. Field of the Invention
The invention relates to a phase lock loop (PLL) apparatus, and more particularly, to the PLL apparatus capable of performing a high-frequency dithering to an index signal to prevent a jitter peak shown in a jitter tolerance curve related to the PLL apparatus.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 shows a scheme diagram of the conventional PLL apparatus. As shown in FIG. 1, the PLL apparatus 1 comprises a phase detector 10, a first charge pump (CP) 12, a second CP 14, a voltage control oscillator 18, and a loop filter (LF) 17 formed by an adder 16, a resistor R, and a capacitor C.
When the phase detector 10 detects the phase difference between an input data signal and a feedback clock signal, the phase detector 10 will generate an up-index or a down-index. On the contrary, if there is no phase difference between the input data signal and the feedback clock signal, the phase detector 10 will not generate the up-index or the down-index. If the up-index is 1, it means that the phase of the feedback clock signal lags the phase of the input data signal; if the down-index is 1, it means that the phase of the feedback clock signal leads the phase of the input data signal. If the current flowing through the first CPLF 12 is I1 and the current flowing through the second CPLF 14 is I2, the control voltage that the voltage control oscillator 18 receives should be I1R+(I2/SC).
Although a probability shaping device can be added in front of the second CPLF 14 in the PLL apparatus 1 to change the frequency of outputting the up-index or the down-index. However, the frequency of outputting the changed up-index or down-index is smaller than the frequency of outputting the unchanged up-index or down-index. Furthermore, this method can not improve the jitter peak shown in certain frequency region of the jitter tolerance curve. For example, in the jitter tolerance curve of the conventional PLL apparatus 1, there will be an obvious jitter peak 62 formed in the corner-band-frequency region which has bad effect on the performance of the PLL apparatus 1.
Therefore, the invention provides a PLL apparatus to solve the above-mentioned problems.